The inventive concepts described herein relate to a semiconductor memory system, and more particularly, to a memory device and a divided clock correction method thereof.
There is demand for electronic devices that provide high performance and low power consumption. As electronic devices are designed to operate at lower power levels, the number of times that a memory system of an electronic device enters into a mode in which the memory system interrupts an operation is increasing.
The memory system may be a volatile memory device or a nonvolatile memory device. A synchronous dynamic random access memory (SDRAM) is a typical example of a volatile memory device. The SDRAM processes input/output data and a command/address signal in synchronization with a clock signal that is provided from a host. The quality of the clock signal may influence the performance of the memory device.
The memory device may enter into a mode in which an operation is interrupted. When such an interruption occurs, the clock signal may not be provided from the host. When the memory device exits from the interrupt mode and resumes normal operation, settings for operation of the memory device may be initialized. Settings of a clock circuit in the memory device may be also initialized when the settings for operation of the memory device are initialized. Accordingly, clock signals that are respectively provided from the memory device and the host may not be synchronized with each other when normal operation resumes after operations were interrupted.